A major benefit of going from a standard five volt EPROM, with a V.sub.cc voltage range of 4.5 to 5.5 volts, to a low voltage EPROM, with an unregulated V.sub.cc voltage range of 2.7 to 3.6, is that the low voltage EPROM consumes much less power. But several problems are encountered when making such a V.sub.cc voltage transition.
First of all, older programming machines, known as EPROM programmers, are designed to program standard five volt EPROMs, and are generally not compatible with newer low voltage EPROMs due primarily to two independent problems. The first problem concerns an EPROM's output drivers. Speed is a major concern for low voltage EPROMs, and an EPROM's output driver is a major component in the determination of an EPROM's read access time. To compensate for a lower V.sub.cc value, low voltage EPROMs incorporate large output drivers with large current driving capabilities which provide for faster rise and fall slew rates at a given vcc value. However, standard EPROM programmers typically use an V.sub.cc value of 6 V or higher to verify a programming instruction. This high V.sub.cc value can cause ringing and signal bouncing in a low voltage EPROM with large output drivers or even damage the EPROM. One way of solving this problem is to reduce the current driving capability of a low voltage EPROM, but this adversely affects the EPROM's speed.
The second problem facing the use of low voltage EPROMs on standard 5 V EPROM programmers is the programmers' algorithm itself. EPROM memories determine the logic level of a storage cell by comparing the amount of current a storage cell can source with a reference current. If the storage cell sources more current than the reference current then it is classified as erased, but if it sources less current than the reference current then it is classified as programmed. It is possible for an erased cell to be partially programmed by an EPROM programmer when it is intended to remain erased. This means that the cell's threshold voltage has been slightly raised, but is still sufficiently low to source enough current for the EPROM programmer to verify the cell as erased when it is verified with V.sub.cc set to 6 V or higher. When the same EPROM is set to function under low voltage V.sub.cc conditions of 2.7 V to 3.6 V, the same memory cell which tested as having been erased under high V.sub.cc conditions may no longer be able to source enough current to read as erased and will instead be read as programmed. Thus it is possible for a cell to verify correct data under high V.sub.cc conditions, but to yield incorrect data under low V.sub.cc conditions. These two problems hinder users of low voltage EPROMs unless users replace or modify their older EPROM programmers to work with low voltage EPROMs.
Furthermore, the benefit of lower power consumption resulting from going from a standard five volt EPROM to a low voltage EPROM is usually accompanied by a degradation in the EPROM's performance. A lower V.sub.cc voltage results in a lower voltage on a cell's word line which translates into a lower memory cell current. A lower memory cell current, in turn, means slower read times since the memory requires more time to determine whether the cell is sourcing enough current to be classified as erased or programmed. This problem not only reduces the speed of the memory, but also reduces manufacturing yield, and generally degrades the overall performance of the memory.
Moreover, low voltage EPROMs may use voltage pumps to raise the memory's internal voltage to a high voltage for programming operations. These voltage pumps are controlled by oscillators which dictate the intervals at which charge is transferred to a voltage pumps's charge storing capacitors. The oscillators are, in turn, very susceptible to V.sub.cc and temperature variations. This, however, has typically not been a problem in prior art EPROMs since the voltage pumps are used only during a programming operation and such operations make up a small fraction of an EPROM's operation time.
Other low voltage memories, such as low voltage EEPROMs and flash EEPROMs, share some of the same problems afflicting low voltage EPROMs. Like low voltage EPROMs, low voltage EEPROMs and flash EEPROMs incorporate large output drivers with high current driving capabilities to compensate for a lower V.sub.cc value. If it is desired to use a low voltage EEPROM or low voltage flash EEPROM within a standard 5 V V.sub.cc environment, the relatively high value of V.sub.cc may cause the large output drivers to have noise problems such as ringing and signal bouncing. Similarly, EEPROMs and flash EEPROMs determine a memory cell's logic level by comparing the memory cell's current sourcing ability with a reference current. Therefore, low voltage EEPROMs and flash EEPROMs suffer from the same problems of slower read times and misread data which afflict low voltage EPROMs, as explained above.
Manufacturers have taken different approaches toward mitigating the adverse effects of low voltage EPROMs. U.S. Pat No. 5,226,013 to Secol et al. describes a means of speeding up an EPROM by precharging a bit line, amplifying the voltage imbalance between the bit line voltage and a reference voltage, and terminating the charging of said bit line as soon as a sensing amplifier has read the cell. U.S. Pat. No. 5,367,206 to Yu et al. discloses an output driver circuit designed to interface a low voltage EPROM with a standard 5 volt EPROM programmer by incorporating circuitry that slows down an output driver during a standard 5 V V.sub.cc programming operation, but speeds up the output driver during low voltage V.sub.cc conditions. U.S. Pat. No. 5,331,295 to Jelinek further describes an oscillator with temperature, voltage, and process compensation. An article in EE Times dated May 10, 1993 discusses an EPROM developed by Toshiba Corp. which can function with V.sub.cc set to a range of 1.5 to 6 volts. The low end voltage of 1.5 V is below the threshold voltage of an EPROM cell, and therefore a word line boost technique is used to raise the word line voltage to a reading voltage of 4 V. The boosted voltage is applied to the word lines through a decoder which switches from a programming voltage of 12.5 V to a reading voltage of 4 V. Although the article did not describe Toshiba's circuitry, it did note that their technique is restricted to consumer or ASIC applications, which have limited EPROM densities.
It is an object of this invention to provide a mechanism for improving the read access time of low voltage non-volatile memories.
It is another object of this invention to provide a low voltage EPROM compatible with standard 5 volt EPROM programmers while providing increased speed and performance.